[SOLVED] Ece210 lab 3:7-segment led decoder
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Students will then learn implementing a binary up counter (0 to F) every second and the value displaying on
7-Segment LED. The 7-Segment LED decoder will be implemented using VHDL, simulation test bench for
verification, implementing it on Zybo Z7 board.Upon completion of this laboratory exercise, students will be able to:
● Implement a 7-segment decoder and display switches (SW0-SW3) data.
● Implement a two-digit decimal up counter.PRELAB
You are expected to read the lab instructions and complete the pre-lab assignments before attending the lab
sessions. You are responsible for submitting your pre-lab assignment in time in the drop-box on eClass.
1. Given the truth table below, Use K-Maps, determine the minimum logical expression for each of the 7
outputs (A through G):
Note: The provided truth table has been
designed in accordance with the inverted
schematic presented in the manual. This is due to
the particular orientation of the Zybo boards
when mounted to the lab bench, which results in
the display of digits in an upside-down fashion.Therefore, be mindful when interpreting the truth
table and correspondingly programming your
display to ensure accurate output, reflecting this
unique setup of the Zybo boards in our lab
environment.2. Draw circuit schematic diagram using minimized logical expressions, either use all AND-OR-NOT logic
or all NAND logic gates.
3. Write and include VHDL solutions in your pre-lab assignment (using VHDL logical operators, such as
AND, OR, etc).4. Please watch the following video to get familiar with implementing a complete truth table using VHDL
conditional statements: VHDL essentials 10 majority architecture.
NOTE: It is very important that you complete the pre-lab components before you come to the lab. Failing to do
so will impede your ability to complete the lab within the allotted time.BACKGROUND
A 7-Segment display as shown below is manufactured using 7-LED’s (segments A, B, C, D, E, F, G), as shown in
Figure 2. An LED (Light Emitting Diode) emits light when the Anode is connected with the positive side of DC
voltage and the cathode is connected with the negative side, as shown below. Such a connection enables current
to flow through the diode, enabling it to emit light.There are two standard types of 7-Segment displays; Common-Anode and Common-Cathode. The 7-Segment
board connected with Zybo Z7 has Common-Cathode configuration, as shown in the schematic below.Common-Anode or Common-Cathode configuration reduces the number of pins necessary to operate the
device, and also provides a global ON or OFF control. In this digital system, logic ‘1’ is equivalent to +3.3 volts
and logic ‘0’ is equivalent to 0 volts.Note: Due to the unique constraints of our
lab setup, specifically the manner in which the
Zybo boards are mounted to the bench, it isn’t
feasible to orient both the seven-segment
display and the keypad in the standard ‘right
side up’ position simultaneously. After careful
consideration, we have opted to adhere to an
upside-down representation to match the
physical orientation of the seven-segment
display on the Zybo board.As you can see both on the schematic above and the 7-Segment board connected to the Zybo Z7, we have two
7-Segments. In order to turn ON a segment on the first 7-Segment:
1. We must first apply logic ‘0’ to the cathode signal (C=>P4 pin), which makes C1 logic ‘1’.
2. Then apply logic ‘1’ to the respective segment (AA to AG) you want to turn ON.To select and display on second 7-Segment, follow these steps:
1. Apply logic ‘1’ to the cathode signal (C=>P4 pin), which makes C2 logic ‘1’.
2. Then apply logic ‘1’ to the respective segment (AA to AG) you want to turn ON.PART 1: 7-SEGMENT DECODER IMPLEMENTATION
1. Download from eClass: design source, constraint file,and simulation test bench.
2. Create a new VHDL project to implement your minimized logical equations for all segments (the pre-lab
work).
3. Demo your work to a TA or LI for a checkoff and present simulation results in your lab report.PART 2: 7-SEGMENT DECODER IMPLEMENTATION USING VHDL
1. Implement 7-segment decoder design using VHDL if-else or case statement. You can find an
introduction to these statements in VHDL in this video:VHDL essentials 10 majority architecture.
2. Demo your works to a TA or LI for a checkoff and present simulation results in your lab report.PART 3: COUNTER FROM 0 TO LAST 2 DIGITS OF STUDENT ID
1. Download from eClass: design source, constraint file, and simulation test bench.
2. Create a new project and complete the design source. Comments in the design source explain what needs
to be done. You are required to simulate and implement an up counter starting from 0 to the last 2 digits
of your student ID in decimal.Note: If the last 2 digits of your student ID are less than 10, please choose any number greater than or
equal to 10.Hint: CC signal can toggle between ‘0’ and ‘1’. While it is zero, you are displaying 4 bits on one 7-
segment. While it is one, you are displaying another 4 bits on the other 7-segment.
3. Demo your work to a TA or LI for checkoff and present simulation results in your lab report.REPORT REQUIREMENTS
1. Simulation results of parts 1 and 2 for digit 0 to F.
2. Codes for parts 1, 2 and 3.
3. Simulation results for part 3. (Showing up counting to the last two digits of your student ID and starting
back from zero. For example, Student ID = *****62)
Note: In order to show signals in your
waveform window, on the scope select
your design source. Right click on the
signal and select Add to waveform window
Note: In order to run the simulation as
long as your student ID, click on 1 to
reset it, then set a time in ns (suggested
time: last 2 digits of your student ID + a
few ns e.g., 65 for someone with the last
two digits equal to 62). Then click on 2
to run the simulation.REFERENCES
● Zybo Z7 Documentation, Tutorials and Example Projects,
● Zybo Z7 Reference Manual
● PMOD Seven Segment display Reference Manual